BIOS

笔记本电脑诊断卡代码

AMIBIOS代码部分

The are reprinted with permission

AMIBIOS 071595 Version 6.24 Following is the checkpoint list in AMIBIOS in order

of execution.

Check Point Description

Uncompressed INIT code checkpoints

D0	NMI is Disabled. CPU ID saved. Init code Checksum verification starting.
D1	To do DMA init, Keyboard controller BAT test, start memory refresh and going to 4GB flat mode.
D3	To start Memory sizing.
D4	To comeback to real mode. Execute OEM patch. Set stack.
D5	E000 ROM enabled. Init code is copied to segment 0 and control to be transfered to segment 0.
D6	Control is in segment 0. To check <CTRL><HOME> key and verify main BIOS checksum. If either <CTRL><HOME> is pressed or main BIOS checksum is bad, go to check point E0 else goto check point D7.
D7	To pass control to Interface Module.
D8	Main BIOS runtime code is to be decompressed.
D9	Control to be passed to main BIOS in shadow RAM.

Boot Block Recovery Code Check Points

E0	OnBoard Floppy Controller (if any) is initialzed. To start base 512K memory test.
E1	To initialise interrupt vector table.
E2	To initialise DMA and interrupt controllers.
E6	To enable floppy and timer IRQ, enable internal cache.
ED	Initialize floppy drive.
EE	Start looking for a diskette in drive A: and read 1st sector of the diskette.
EF	Floppy read error.
F0	Start searching 'MIBOOT.ROM' file in root directory.
F1	'AMIBOOT.ROM' file not present in root directory.
F2	Start reading FAT table and analyze FAT to find the clusters occupied by 'AMIBOOT.ROM' file..
F3	Start reading 'MIBOOT.ROM' file cluster by cluster.
F4	'AMIBOOT.ROM' file not of proper size.
F5	Disable internal cache.
FB	Detect Flash type present.
FC	Erase Flash.
FD	Program Flash.
FF	Flash program successful. BIOS is going to restart.

Runtime code is uncompressed in F000 shadow ram

03	NMI is Disabled. To check soft reset/power-on.
05	BIOS stack set. Going to disable Cache if any.
06	POST code to be uncompressed.
07	CPU init and CPU data area init to be done.
08	CMOS checksum calculation to be done next.
0B	Any initialization before keyboard BAT to be done next.
0C	KB controller I/B free. To issue the BAT command to keyboard controller.
0E	Any initialization after KB controller BAT to be done next.
0F	Keyboard command byte to be written.
10	Going to issue Pin-23,24 blocking/unblocking command.
11	Going to check pressing of <INS> , <END> key during power-on.
12	To init CMOS if "Init CMOS in every boot" is set or <END> key is pressed. Going to disable DMA and Interrupt controllers.
13	Video display is disabled and port-B is initialized. Chipset init about to begin.
14	8254 timer test about to start.
19	About to start memory refresh test.
1A	Memory Refresh line is toggling. Going to check 15us ON/OFF time.
23	To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment writeable.
24	To do any setup before Int vector init.
25	Interrupt vector initialization about to begin. To clear password if necessary.
27	Any initialization before setting video mode to be done.
28	Going for monochrome mode and color mode setting.
2A	Different BUSes init (system, static, output devices) to start if present. (Please see Appendix for details of different BUSes).
2B	To give control for any setup required before optional video ROM check.
2C	To look for optional video ROM and give control.
2D	To give control to do any processing after video ROM returns control.
2E	If EGA/VGA not found then do display memory R/W test.
2F	EGA/VGA not found. Display memory R/W test about to begin.
30	Display memory R/W test passed. About to look for the retrace checking.
31	Display memory R/W test or retrace checking failed. To do alternate Display memory R/W test.
32	Alternate Display memory R/W test passed. To look for the alternate display retrace checking.
34	Video display checking over. Display mode to be set next.
37	Display mode set. Going to display the power on message.
38	Different BUSes init (input, IPL, general devices) to start if present. (Please see Appendix for details of different BUSes).
39	Display different BUSes initialization error messages. (Please see Appendix for details of different BUSes).
3A	New cursor position read and saved. To display the Hit <DEL> message.
40	To prepare the descriptor tables.
42	To enter in virtual mode for memory test.
43	To enable interrupts for diagnostics mode.
44	To initialize data to check memory wrap around at 0:0.
45	Data initialized. Going to check for memory wrap around at 0:0 and finding the total system memory size.
46	Memory wrap around test done. Memory size calculation over. About to go for writing patterns to test memory.
47	Pattern to be tested written in extended memory. Going to write patterns in base 640k memory.
48	Patterns written in base memory. Going to findout amount of memory below 1M memory.
49	Amount of memory below 1M found and verified. Going to findout amount of memory above 1M memory.
4B	Amount of memory above 1M found and verified. Check for soft reset and going to clear memory below 1M for soft reset. (If power on, go to check point# 4Eh).
4C	Memory below 1M cleared. (SOFT RESET) Going to clear memory above 1M.
4D	Memory above 1M cleared. (SOFT RESET) Going to save the memory size. (Goto check point# 52h).
4E	Memory test started. (NOT SOFT RESET) About to display the first 64k memory size.
4F	Memory size display started. This will be updated during memory test. Going for sequential and random memory test.
50	Memory testing/initialization below 1M complete. Going to adjust displayed memory size for relocation/shadow.
51	Memory size display adjusted due to relocation/ shadow. Memory test above 1M to follow.
52	Memory testing/initialization above 1M complete. Going to save memory size information.
53	Memory size information is saved.CPU registers are saved. Going to enter in real mode.
54	Shutdown successful, CPU in real mode. Going to disable gate A20 line and disable parity/NMI.
57	A20 address line, parity/NMI disable successful. Going to adjust memory size depending on relocation/shadow.
58	Memory size adjusted for relocation/shadow. Going to clear Hit <DEL> message.
59	Hit <DEL> message cleared. <WAIT...> message displayed. About to start DMA and interrupt controller test.
60	DMA page register test passed. To do DMA#1 base register test.
62	DMA#1 base register test passed. To do DMA#2 base register test.
65	DMA#2 base register test passed. To program DMA unit 1 and 2.
66	DMA unit 1 and 2 programming over. To initialize 8259 interrupt controller.
7F	Extended NMI sources enabling is in progress.
80	Keyboard test started. clearing output buffer, checking for stuck key, to issue keyboard reset command.
81	Keyboard reset error/stuck key found. To issue keyboard controller interface test command.
82	Keyboard controller interface test over. To write command byte and init circular buffer.
83	Command byte written, Global data init done. To check for lock-key.
84	Lock-key checking over. To check for memory size mismatch with CMOS.
85	Memory size check done. To display soft error and check for password or bypass setup.
86	Password checked. About to do programming before setup.
87	Programming before setup complete. To uncompress SETUP code and execute CMOS setup.
88	Returned from CMOS setup program and screen is cleared. About to do programming after setup.
89	Programming after setup complete. Going to display power on screen message.
8B	First screen message displayed. <WAIT...> message displayed. PS/2 Mouse check and extended BIOS data area allocation to be done.
8C	Setup options programming after CMOS setup about to start.
8D	Going for hard disk controller reset.
8F	Hard disk controller reset done. Floppy setup to be done next.
91	Floppy setup complete. Hard disk setup to be done next.
95	Init of different BUSes optional ROMs from C800 to start. (Please see Appendix-I for details of different BUSes).
96	Going to do any init before C800 optional ROM control.
97	Any init before C800 optional ROM control is over. Optional ROM check and control will be done next.
98	Optional ROM control is done. About to give control to do any required processing after optional ROM returns control and enable external cache.
99	Any initialization required after optional ROM test over. Going to setup timer data area and printer base address.
9A	Return after setting timer and printer base address. Going to set the RS-232 base address.
9B	Returned after RS-232 base address. Going to do any initialization before Coprocessor test.
9C	Required initialization before Coprocessor is over. Going to initialize the Coprocessor next.
9D	Coprocesor initialized. Going to do any initialization after Coprocessor test.
9E	Initialization after Coprocessor test is complete. Going to check extd keyboard, keyboard ID and num-lock.
9F	Keyboard ID command to be issued.
A2	Going to display any soft errors.
A3	Soft error display complete. Going to set keyboard typematic rate.
A4	Keyboard typematic rate set. To program memory wait states.
A5	Going to enable parity/NMI.
A7	NMI and parity enabled. Going to do any initialization required before giving control to optional ROM at E000.
A8	Initialization before E000 ROM control over. E000 ROM to get control next.
A9	Returned from E000 ROM control. Going to do any initialization required after E000 optional ROM control.
AA	Initialization after E000 optional ROM control is over. Going to display the system configuration.
AB	To build MP table if needed.
AC	To uncompress DMI data and execute DMI POST init.
B0	System configuration is displayed.
B1	Going to copy any code to specific area.
00	Copying of code to specific area done. Going to give control to INT-19 boot loader.

APPENDIX

The system BIOS gives control to the different BUSes at following checkpoints to do

various tasks on the different BUSes.

Check Point Description

2A	Different BUSes init (system, static, output devices) to start if present.
38	Different BUSes init (input, IPL, general devices) to start if present.
39	Display different BUSes initialization error messages.
95	Init of different BUSes optional ROMs from C800 to start.

While control is inside the different BUS routines, additionalcheckpoints are output to

port 80h as WORD to identify the routines under execution. These are WORD

checkpoints, the LOW BYTE of checkpoint is the system BIOS checkpoint from where

the control is passed to the different BUS routines and the HIGH BYTE of checkpoint

is the indication of which routine is being executed in different BUSes. The details of

HIGH BYTE of these checkpoints are as follows:

HIGH BYTE XY

the upper nibble 'X' indicates the function# is being executed. 'X' can be from 0 to 7.

0 =	func#0, disable all devices on the BUS concerned.
1 =	func#1, static devices init on the BUS concerned.
2 =	func#2, output device init on the BUS concerned.
3 =	func#3, input device init on the BUS concerned.
4 =	func#4, IPL device init on the BUS concerned.
5 =	func#5, general device init on the BUS concerned.
6 =	func#6, error reporting for the BUS concerned.
7 =	func#7, add-on ROM init for all BUSes.

the lower nibble 'Y' indicates the BUS on which the different routines are being

executed. 'Y' can be from 0 to 5.

0 =	Generic DIM (Device Initialization Manager).
1 =	On-board System devices.
2 =	ISA devices.
3 =	EISA devices.
4 =	ISA PnP devices.
5 =	PCI devices.

American Megatrends Inc.

PhoenixBIOS系列

Title: PhoenixBIOS 4.0 Error Beep Codes

Filename: BEEP4.TXT

WWW URL: http://www.firmware.com/pb4ts/beep4.htm

FTP URL: ftp://ftp.firmware.com/text/beep4.txt

Revision: 05/20/97

Summary: Listing of error codes (port 80h hex values and 4-part beep codes) used by Phoenix 4.x BIOSes.

==================================================================

As the power-on self test progresses, numeric values representing the status of the test

are sent to port 80h. There are many diagnostic boards (also called POST boards or

cards) on the market today which plug in to the PC expansion bus and have a dual LED

display which decodes and displays the value at port 80h. With a POST board installed,

you can monitor the progress of the self-test as it progresses. Not all tests listed in the

table below will be executed on all systems, nor will they always be executed in order.

If a fatal error occurs, the PhoenixBIOS 4.0 will attempt to issue a beep code

representing the error, and it will also attempt to display the error code on a

monochrome or CGA display. In the event of a fatal system error during initialization,

the code representing the portion of the POST causing the failure will be the last value

sent to port 80h. As any experienced technician knows, a failure at any given location

does not necessarily mean that the particular part or section under test has actually

failed.

If you require further details or assistance in dealing with a fatal system board error,

please do not contact Micro Micro Firmware. You need to seek the assistance of a

qualified computer service technician in your area.

This POST/BEEP code list is applicable only to PhoenixBIOS 4.x

For Phoenix ROM BIOS PLUS or PhoenixBIOS 1.xx, see BEEP3.TXT.

Beep code	POST code	Description/test point
1-1-1-3	02	Verify Real Mode
1-1-2-1	04	Get CPU type
1-1-2-3	06	Initialize system hardware
1-1-3-1	08	Initialize chipset registers with initial POST values
1-1-3-2	09	Set in POST flag
1-1-3-3	0A	Initialize CPU registers
1-1-4-1	0C	Initialize cache to initial POST values
1-1-4-3	0E	Initialize I/O
1-2-1-1	10	Initialize Power Management
1-2-1-2	11	Load alternate registers with initial POST values
1-2-1-3	12	Jump to UserPatch0
1-2-2-1	14	Initialize keyboard controller
1-2-2-3	16	BIOS ROM checksum
1-2-3-1	18	8254 timer initialization
1-2-3-3	1A	8237 DMA controller initialization
1-2-4-1	1C	Reset Programmable Interrupt Controller
1-3-1-1	20	Test DRAM refresh
1-3-1-3	22	Test 8742 Keyboard Controller
1-3-2-1	24	Set ES segment to register to 4 GB
1-3-3-1	28	Autosize DRAM
1-3-3-3	2A	Clear 512K base RAM
1-3-4-1	2C	Test 512 base address lines
1-3-4-3	2E	Test 512K base memory
1-4-1-3	32	Test CPU bus-clock frequency
1-4-2-1	34	CMOS RAM read/write failure (this commonly indicates a problem on the ISA bus such as a card not seated correctly)
1-4-2-4	37	Reinitialize the chipset
1-4-3-1	38	Shadow system BIOS ROM
1-4-3-2	39	Reinitialize the cache
1-4-3-3	3A	Autosize cache
1-4-4-1	3C	Configure advanced chipset registers
1-4-4-2	3D	Load alternate registers with CMOS values
2-1-1-1	40	Set Initial CPU speed
2-1-1-3	42	Initialize interrupt vectors
2-1-2-1	44	Initialize BIOS interrupts
2-1-2-3	46	Check ROM copyright notice
2-1-2-4	47	Initialize manager for PCI Options ROMs
2-1-3-1	48	Check video configuration against CMOS
2-1-3-2	49	Initialize PCI bus and devices
2-1-3-3	4A	Initialize all video adapters in system
2-1-4-1	4C	Shadow video BIOS ROM
2-1-4-3	4E	Display copyright notice
2-2-1-1	50	Display CPU type and speed
2-2-1-3	52	Test keyboard
2-2-2-1	54	Set key click if enabled
2-2-2-3	56	Enable keyboard
2-2-3-1	58	Test for unexpected interrupts
2-2-3-3	5A	Display prompt "Press F2 to enter SETUP"
2-2-4-1	5C	Test RAM between 512 and 640k
2-3-1-1	60	Test expanded memory
2-3-1-3	62	Test extended memory address lines
2-3-2-1	64	Jump to UserPatch1
2-3-2-3	66	Configure advanced cache registers
2-3-3-1	68	Enable external and CPU caches
2-3-3-2	69	Initialize SMI handler
2-3-3-3	6A	Display external cache size
2-3-4-1	6C	Display shadow message
2-3-4-3	6E	Display non-disposable segments
2-4-1-1	70	Display error messages
2-4-1-3	72	Check for configuration errors
2-4-2-1	74	Test real-time clock
2-4-2-3	76	Check for keyboard errors
2-4-4-1	7C	Set up hardware interrupts vectors
2-4-4-3	7E	Test coprocessor if present
3-1-1-1	80	Disable onboard I/O ports
3-1-1-3	82	Detect and install external RS232 ports
3-1-2-1	84	Detect and install external parallel ports
3-1-2-3	86	Re-initialize onboard I/O ports
3-1-3-1	88	Initialize BIOS Data Area
3-1-3-3	8A	Initialize Extended BIOS Data Area
3-1-4-1	8C	Initialize floppy controller
3-2-1-1	90	Initialize hard-disk controller
3-2-1-2	91	Initialize local-bus hard-disk controller
3-2-1-3	92	Jump to UserPatch2
3-2-2-1	94	Disable A20 address line
3-2-2-3	96	Clear huge ES segment register
3-2-3-1	98	Search for option ROMs
3-2-3-3	9A	Shadow option ROMs
3-2-4-1	9C	Set up Power Management
3-2-4-3	9E	Enable hardware interrupts
3-3-1-1	A0	Set time of day
3-3-1-3	A2	Check key lock
3-3-3-1	A8	Erase F2 prompt
3-3-3-3	AA	Scan for F2 key stroke
3-3-4-1	AC	Enter SETUP
3-3-4-3	AE	Clear in-POST flag
3-4-1-1	B0	Check for errors
3-4-1-3	B2	POST done--prepare to boot operating system
3-4-2-1	B4	One beep
3-4-2-3	B6	Check password (optional)
3-4-3-1	B8	Clear global descriptor table
3-4-4-1	BC	Clear parity checkers
3-4-4-3	BE	Clear screen (optional)
3-4-4-4	BF	Check virus and backup reminders
4-1-1-1	C0	Try to boot with INT 19
4-2-1-1	D0	Interrupt handler error
4-2-1-3	D2	Unknown interrupt error
4-2-2-1	D4	Pending interrupt error
4-2-2-3	D6	Initialize option ROM error
4-2-3-1	D8	Shutdown error
4-2-3-3	DA	Extended Block Move
4-2-4-1	DC	Shutdown 10 error
4-2-4-3	DE	Keyboard Controller Failure (most likely problem is with RAM or cache unless no video is present)
4-3-1-3	E2	Initialize the chipset
4-3-1-4	E3	Initialize refresh counter
4-3-2-1	E4	Check for Forced Flash
4-3-2-2	E5	Check HW status of ROM
4-3-2-3	E6	BIOS ROM is OK
4-3-2-4	E7	Do a complete RAM test
4-3-3-1	E8	Do OEM initialization
4-3-3-2	E9	Initialize interrupt controller
4-3-3-3	EA	Read in bootstrap code
4-3-3-4	EB	Initialize all vectors
4-3-4-1	EC	Boot the Flash program
4-3-4-2	ED	Initialize the boot device
4-3-4-3	EE	Boot code was read OK

Award系列

he are reprinted with permission

Award Software International EliteBIOS? Version 4.51PG

POST Codes NOTE: EISA POST codes are typically output to port address 300h.

ISA POST codes are output to port address 80h.

Code (hex)	Name	Description
C0	Turn Off Chipset Cache	OEM Specific-Cache control
01	Processor Test 1	Processor Status (1FLAGS)Verification. Tests the following processor status flags: carry, zero, sign, overflow, The BIOS sets each flag, verifies they are set, then turns each flag off and verifies it is off.
02	Processor Test 2	Read/Write/Verify all CPU registers except SS, SP, and BP with data pattern FF and 00.
03	Initialize Chips	Disable NMI, PIE, AIE, UEI, SQWV. Disable video, parity checking, DMA. Reset math coprocessor. Clear all page registers, CMOS shutdown byte. Initialize timer 0, 1, and 2, including set EISA timer to a known state. Initialize DMA controllers 0 and 1. Initialize interrupt controllers 0 and 1 Initialize EISA extended registers.
04	Test Memory Refresh Toggle	RAM must be periodically refreshed to keep the memory from decaying. This function ensures that the memory refresh function is working properly.
05	Blank video, Initialize keyboard	Keyboard controller initialization.
06	Reserved
07	Test CMOS Interface and Battery Status	Verifies CMOS is working correctly, detects bad battery.
BE	Chipset Default Initialization	Program chipset registers with power on BIOS defaults.
C1	Memory presence test	OEM Specific-Test to size on-board memory
C5	Early Shadow	OEM Specific-Early Shadow enable for fast boot.
C6	Cache presence test	External cache size detection
08	Setup low memory	Early chip set initialization. Memory presence test OEM chip set routines. Clear low 64K of memory. Test first 64K memory.
09	Early Cache Initialization	Cyrix CPU initialization. Cache initialization.
0A	Setup Interrupt Vector Table	Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR and initialize INT 00h-1Fh according to INT_TBL
0B	Test CMOS RAM Checksum	Test CMOS RAM Checksum, if bad, or insert key pressed, load defaults.
0C	Initialize keyboard	Detect type of keyboard controller (optional). Set NUM_LOCK status.
0D	Initialize Video Interface	Detect CPU clock. Read CMOS location 14h to find out type of video in use. Detect and Initialize Video Adapter.
0E	Test Video Memory	Test video memory, write sign-on message to screen. Setup shadow RAM - Enable shadow according to Setup.
0F	Test DMA Controller 0	BIOS checksum test. Keyboard detect and initialization
10	Test DMA Controller 1
11	Test DMA Page Registers	Test DMA Page Registers.
12-13	Reserved
14	Test Timer Counter 2	Test 8254 Timer 0 Counter 2.
15	Test 8259-1 Mask Bits	Verify 8259 Channel 1 masked interrupts by alternately turning off and on the interrupt lines.
16	Test 8259-2 Mask Bits	Verify 8259 Channel 2 masked interrupts by alternately turning off and on the interrupt lines.
17	Test Stuck 8259's Interrupt Bits	Turn off interrupts then verify no interrupt mask register is on.
18	Test 8259 Interrupt Functionality	Force an interrupt and verify the interrupt occurred.
19	Test Stuck NMI Bits (Parity/IO Check)	Verify NMI can be cleared.
1A		Display CPU clock
1B-1E		Reserved
1F	Set EISA Mode	If EISA non-volatile memory checksum is good, execute EISA initialization. If not, execute ISA tests an clear EISA mode flag. Test EISA Configuration Memory Integrity (checksum & communication interface).
20	Enable Slot 0	Initialize slot 0 (System Board).
21-2F	Enable Slots 1-15	Initialize slots 1 through 15.
30	Size Base and Extended Memory	Size base memory from 256K to 640K and extended memory above 1MB.
31	Test Base and Extended Memory	Test base memory from 256K to 640K and extended memory above 1MB using various patterns. NOTE: This test is skipped in EISA mode and can be skipped with ESC key in ISA mode.
32	Test EISA Extended Memory	If EISA Mode flag is set then test EISA memory found in slots initialization. NOTE: This test is skipped in ISA mode and can be skipped with ESC key in EISA mode.
33-3B	Reserved
3C	Setup Enabled
3D	Initialize & Install Mouse	Detect if mouse is present, initialize mouse, install interrupt vectors.
3E	Setup Cache Controller	Initialize cache controller.
3F	Reserved
BF	Chipset Initialization	Program chipset registers with Setup values
40		Display virus protect disable or enable
41	Initialize Floppy Drive & Controller	Initialize floppy disk drive controller and any drives.
42	Initialize Hard Drive & Controller	initialize hard drive controller and any drives.
43	Detect & Initialize Serial/Parallel Ports	Initialize any serial and parallel ports (also game port).
44	Reserved
45	Detect & Initialize Math Coprocessor	Initialize math coprocessor.
46	Reserved
47	Reserved
48-4D	Reserved
4E	Manufacturing POST Loop or Display Messages	Reboot if Manufacturing POST Loop pin is set. Otherwise display any messages (i.e., any non-fatal errors that were detected during POST) and enter Setup.
4F	Security Check	Ask password security (optional).
50	Write CMOS	Write all CMOS values back to RAM and clear screen.
51	Pre-boot Enable	Enable parity checker. EnableNMI, Enable cache before boot.
52	Initialize Option ROMs	Initialize any option ROMs present from C8000h to EFFFFh. NOTE: When FSCAN option is enabled, ROMs initialize from C8000h to F7FFFh.
53	Initialize Time Value	Initialize time value in 40h: BIOS area.
60	Setup Virus Protect	Setup virus protect according to Setup
61	Set Boot Speed	Set system speed for boot
62	Setup NumLock	Setup NumLock status according to Setup
63	Boot Attempt	Set low stack. Boot via INT 19h.
B0	Spurious	If interrupt occurs in protected mode.
B1	Unclaimed NMI	If unmasked NMI occurs, display Press F1 to disable NMI, F2 reboot.
E1-EF	Setup Pages	E1- Page 1, E2 - Page 2, etc.
FF	Boot

EliteBIOS is a trademark of Award Software International Inc.

Award Software International and the Award logo are registered trademarks of Award Software International Inc.

All other products and brand names are trademarks and registered trademarks of their respective companies.

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