| SYMBOL |
FUNCTION |
| 3.3V |
3.3V power supply. |
| VCC |
5V power supply. |
| 12V |
12V power supply. |
| GND |
Ground pins |
| -5V |
-5V power supply. |
| -12V |
-12V power supply. |
| AD[31:0] |
PCI
Bus Address and Data Signals.
The standard PCI address and
data lines. Address is driven with FRAME# assertion, data is
driven or received in following clocks. |
| C/BE[3:0]# |
PCI Bus Command and Byte Enables.
During the address phase
of a transaction C/BE[3:0]# define the bus command.During the data phase
C/BE[3:0]# are used as Byte Enables.
|
| FRAME# |
Frame Signal.
FRAME# is driven by the current PCI bus master to
indicate the beginning and duration of
an access.
|
| IDSEL |
Initialization Device Select.
IDSEL is used as a chip select during configuration read and write
transactions. This signal should be externally tied to one of the upper
21 address signals.
|
| STOP# |
Bus Stop#.
STOP# indicates the current target is requesting the master to stop the
current PCI bus transaction.
|
| IRDY# |
Initiator Ready.
IRDY# indicates the initiating agent ability to complete the current
data phase of the PCI bus transaction.
|
| TRDY# |
Target Ready.
TRDY# indicates the target agent
ability to complete the
current data phase of the PCI bus transaction.
|
| DEVSEL# |
Device Select.
DEVSEL# to indicate that it is the target of the current PCI bus
transaction.
|
| SERR# |
System Error.
SERR# can be pulsed active by any PCI agent that detects a system error
condition.
|
| PAR |
Parity Signal.
Generates even parity across AD[31:0] and
C/BE[3:0]#.
|
| PCIRST# |
PCI Reset.
Receives PCIRST# as a reset from the PCI Bus.
|
